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1 ltc1879 1879f 1.2a synchronous step-down regulator with 15 m a quiescent current n cellular telephones n portable computers n wireless modems , ltc and lt are registered trademarks of linear technology corporation. high efficiency step-down converter n high efficiency: up to 95% n low quiescent current: only 15 m a with no load n 550khz constant frequency operation n 2.65v to 10v input voltage range n v out from 0.8v to v in , i out to 1.2a n true pll frequency locking from 350khz to 750khz n power good output voltage monitor n low dropout operation: 100% duty cycle n burst mode ? or pulse skipping operation n current mode operation for excellent line and load transient response n shutdown mode draws < 1 m a supply current n 2% output voltage accuracy n overcurrent and overtemperature protected n available in 16-lead ssop package the ltc ? 1879 is a high efficiency monolithic synchro- nous buck regulator using a constant frequency, current mode architecture. operating supply current is only 15 m a with no load and drops to < 1 m a in shutdown. the input supply voltage range of 2.65v to 10v makes the ltc1879 ideally suited for both single and dual li-ion battery-pow- ered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. the switching frequency is internally set to 550khz, allow- ing the use of small surface mount inductors and capaci- tors. for noise sensitive applications, the ltc1879 can be externally synchronized from 350khz to 750khz. burst mode operation is inhibited during synchronization or when the sync/mode pin is pulled low. the internal synchronous rectifier switch increases effi- ciency and eliminates the need for an external schottky diode. low output voltages are easily supported with a 0.8v feedback reference voltage. the ltc1879 is available in a 16-lead ssop package. burst mode is a registered trademark of linear technology corporation. efficiency vs output load current run/ss sync/mode pgood i th 2 15 14 4 pv in swp swn pgnd v fb 8, 9 5, 12 6, 11 7, 10 3 sv in 13 ltc1879 28.0k c in : taiyo yuden ceramic lmk325bj106mn c out : tdk ceramic c4532x5roj476m l1: toko a921cy6r2m *v out connected to v in (minus switch and l1 voltage drop) for 2.65v < v in < 3.1v 1879 ta01a 1 220pf 150k 80.6k c out 47 f v out * 3.1v l1 6.2 h sgnd 47pf c in 10 f v in 2.65v to 10v ouput current (ma) efficiency (%) 100 90 80 70 60 50 40 30 0.1 10 100 1879 ta01b 1 1000 burst mode operation v out = 3.1v l = 6.2 h v in = 7.2v v in = 10v v in = 3.6v features descriptio u applicatio s u typical applicatio u
2 ltc1879 1879f symbol parameter conditions min typ max units i vfb feedback current (note 4) l 860 na v fb regulated output voltage (note 4) 0 c t a 85 c 0.784 0.80 0.816 v (note 4) C 40 c t a 85 c l 0.740 0.80 0.840 v d v ovl overvoltage trip limit with respect to v fb d v ovl = v ovl C v fb l 20 60 110 mv d v uvl undervoltage trip limit with respect to v fb d v uvl = v fb C v uvl l 20 60 110 mv d v fb /v fb reference voltage line regulation v in = 2.65v to 10v (note 4) 0.05 0.25 %/v v loadreg output voltage load regulation measured in servo loop, v ith = 0.9v to 1.2v l 0.1 0.6 % measured in servo loop, v ith = 1.6v to 1.2v l C 0.1 C 0.6 % v in input voltage range l 2.65 10 v i q input dc bias current (note 5) pulse skipping mode 2.65v < v in < 10v, v sync/mode = 0v, i out = 0a 270 365 m a burst mode operation v sync/mode = v in , i out = 0a 15 22 m a shutdown v run = 0v, v in = 10v 0 1 m a f sync sync capture range 350 750 khz f osc oscillator frequency v fb 3 0.7v 495 550 605 khz v fb = 0v 80 khz i plllpf phase detector output current sinking capability f pllin < f osc l 3 10 20 m a sourcing capability f pplin > f soc l C3 C10 C20 m a r pfet r ds(on) of p-channel fet i sw = 100ma, v in = 5v 0.35 0.45 w r nfet r ds(on) of n-channel fet i sw = C 100ma, v in = 5v 0.37 0.5 w i pk peak inductor current v fb = 0.7v, duty cycle < 35%, v in = 5v 1.8 2.2 2.7 a i lsw sw leakage v run = 0v, v sw = 0v or 10v, v in = 10v 0.01 2.5 m a v sync/mode sync/mode threshold l 0.2 1.0 1.5 v i sync/mode sync/mode leakage current 0.01 1 m a (note 1) order part number LTC1879EGN t jmax = 125 c, q ja = 140 c/ w, q jc = 40 c/ w the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 5v unless otherwise noted. absolute m axi m u m ratings w ww u package/order i n for m atio n w u u electrical characteristics input supply voltage ................................ C 0.3v to 11v i th , pll_lpf voltages ............................. C 0.3v to 2.7v run/ss, v fb voltages ............................... C 0.3v to v in sync/mode voltage ................................. C 0.3v to v in (v pvin C v swp ) voltage ............................. C 0.3v to 11v v swn voltage ............................................ C 0.3v to 11v p-channel switch source current (dc) .................... 2a n-channel switch sink current (dc) ........................ 2a peak switching sink and source current ................. 3a operating ambient temperature range (note 2) ............................................. C 40 c to 85 c junction temperature (notes 3, 6) ...................... 125 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 sgnd run/ss v fb i th swp1 swn1 pgnd1 pv in1 pll_lpf sync/mode pgood sv in swp2 swn2 pgnd2 pv in2 gn part marking 1879 consult ltc marketing for parts specified with wider operating temperature ranges.
3 ltc1879 1879f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v in = 5v unless otherwise noted. electrical characteristics v run run threshold v run ramping up l 0.2 0.7 1.5 v i run run input current v run = 0v 0.01 1 m a note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltc1879e is guaranteed to meet specified performance from 0 c to 70 c. specifications over the C 40 c to 85 c operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: ltc1879: t j = t a + (p d 140 c/w) note 4: the ltc1879 is tested in a feedback loop which servos v fb to the balance point for the error amplifier (v ith = 1.2v) note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125 c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. r ds(on) vs temperature oscillator frequency vs temperature oscillator frequency vs supply voltage typical perfor a ce characteristics uw dc supply current vs temperature symbol parameter conditions min typ max units r ds(on) vs input voltage temperature ( c) 50 25 0 25 50 75 100 125 r ds(on) ( ) 1879 g01 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v in = 5v v in = 5v v in = 10v v in = 10v synchronous switch main switch temperature ( c) 50 25 0 25 50 75 100 125 frequency (khz) 1879 g02 595 575 555 535 515 495 v in = 5v supply voltage (v) 2 4 6810 oscillator frequency (khz) 1879 g03 600 590 580 570 560 550 540 530 520 510 500 temperature ( c) ?0 0 50 100 125 supply current ( a) 1879 g04 300 250 200 150 100 50 0 pulse skipping mode burst mode operaton v in = 5v dc supply current vs input voltage input voltage (v) 0 0 dc supply current ( a) 50 100 150 200 250 300 2468 1879 g05 10 pulse skipping mode burst mode operation input voltage (v) 2 0 r ds(on) ( ) 0.1 0.2 0.3 0.4 46 8 10 1879 g06 0.5 0.6 35 7 9 synchronous switch main switch
4 ltc1879 1879f typical perfor a ce characteristics uw switch leakage vs temperature efficiency vs output current efficiency vs input voltage efficiency vs output current temperature ( c) ?0 0 switch leakage ( a) 2 6 8 10 20 14 0 50 75 1879 g07 4 16 18 12 ?5 25 100 125 v in = 10v main switch synchronous switch input voltage (v) 0 switch leakage (na) 30 40 50 8 1879 g08 20 10 25 35 45 15 5 0 2 4 6 10 run = 0v t a = 25 c synchronous switch main switch switch leakage vs input voltage output voltage vs load current load current (ma) 0 2.41 output voltage (v) 2.42 2.44 2.45 2.46 2.51 2.48 400 800 1000 1879 g09 2.43 2.49 2.50 2.47 200 600 1200 1400 1600 pulse skipping mode v in = 5v l = 6.2 h reference voltage vs temperature temperature ( c) 50 25 0 25 50 75 100 125 reference voltage (mv) 1879 g10 804 803 802 801 800 799 798 797 796 795 794 v in = 6v output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 0.1 10 100 1879 g11 1 1000 v in = 10v v in = 3.6v v out = 1.8v l = 6.2 h burst mode operation v in = 5v v in = 7.2v output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 0.1 10 100 1879 g12 1 1000 v in = 10v v in = 3.6v v out = 2.5v l = 6.2 h burst mode operation v in = 7.2v v in = 5v efficiency vs output current output current (ma) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 0.1 10 100 1879 g13 1 1000 v out = 3.1v l = 6.2 h burst mode operation pulse skipping mode v in = 4.2v v in = 4.2v v in = 7.2v v in = 7.2v input voltage (v) 2 70 80 100 8 1879 g14 60 0.1ma 1ma 100ma 10ma 50 46 10 40 30 90 efficiency (%) v out = 2.5v l = 6.2 h burst mode operation
5 ltc1879 1879f load step (pulse skipping mode) pulse skipping mode operation burst mode operation typical perfor a ce characteristics uw i l 200ma/div v out 20mv/div sw 5v/div v out 100mv/div i l 1a/div i l 200ma/div v out 50mv/div sw 5v/div 50 m s/div 1879 g16 v in = 5v c in = 20 m f v out = 2.5v c out = 47 m f l = 4.7 m hi load = 50ma to 1200ma 2.5 m s/div 1879 g17 v in = 5v c in = 20 m f v out = 2.5v c out = 47 m f l = 4.7 m hi load = 15ma 25 m s/div 1879 g18 v in = 5v c in = 20 m f v out = 2.5v c out = 47 m f l = 4.7 m hi load = 15ma load step (burst mode operation) v out 100mv/div i l 1a/div 50 m s/div 1879 g15 v in = 5v c in = 20 m f v out = 2.5v c out = 47 m f l = 4.7 m hi load = 50ma to 1200ma soft-start with shorted output i vin 500ma/div run/ss 1v/div 5ms/div 1879 g19 v in = 5v c in = 20 m f v out = 0v c out = 47 m f l = 4.7 m hi load = 0a
6 ltc1879 1879f uu u pi fu ctio s sgnd (pin 1): signal ground pin. run/ss (pin 2): combination of soft-start and run control inputs. forcing this pin below 0.7v shuts down the device. in shutdown all functions are disabled and device draws zero supply current. for the proper operation of the part, force this pin above 2.5v. do not leave this pin floating. soft-start can be accomplished by raising the voltage on this pin gradually with an rc circuit. v fb (pin 3): feedback pin. receives the feedback voltage from an external resistor divider across the output. i th (pin 4): error amplifier compensation point. the current output increases with this control voltage. nomi- nal voltage range for this pin is 0.5v to 1.8v. swp1, swp2 (pins 5, 12): upper switch nodes. these pins connect to the drains of the internal main pmos switches and should always be connected together externally. swn1, swn2 (pins 6, 11): lower switch nodes. these pins connect to the drains of the internal synchronous nmos switches and should always be connected together externally. pgnd1, pgnd2 (pins 7, 10): power ground pins. ground pins for the internal drivers and switches. these pins should always be tied together. pv in1 , pv in2 (pins 8, 9): power supply pins for the internal drivers and switches. these pins should always be tied together. sv in (pin 13): signal power supply pin. pgood (pin 14): power good indicator pin. power good is an open-drain logic output. the pgood pin is pulled to ground when the voltage on the v fb pin is not within 7.5% of its nominally regulated potential. this pin re- quires a pull-up resistor for power good indication. power good indication works in all modes of operation. sync/mode (pin 15): external clock synchronization and mode select input. to synchronize, apply an external clock with a frequency between 350khz and 750khz. to select burst mode operation, tie pin to sv in . grounding this pin selects pulse skipping mode. do not leave this pin floating. pll_lpf (pin 16): output of the phase detector and control input of oscillator. connect a series rc lowpass network from this pin to ground if externally synchronized. if unused, this pin may be left open.
7 ltc1879 1879f block diagra w + + + + + ea i th burst sleep en sleep 0.8v 0.86v 0.6v v fb sv in freq shift slope comp osc vco and osc x burst defeat y y = ??only when x is a constant ? run/ss sync/mode pll_lpf s r rs latch q 0.45v q switching logic and blanking circuit thermal shutdown anti- shoot- through ovdet ov + rcmp + 0.74v uvdet pgood shutdown sgnd soft-start 0.8v ref sv in + i comp 2.9 pgnd 7, 10 6, 11 8, 9 top mosfet bottom mosfet 1879 bd swn pv in sv in 0.8v 14 1 4 16 15 3 2 13 5, 12 swp
8 ltc1879 1879f operatio u main control loop the ltc1879 uses a constant frequency, current mode step-down architecture. both the top mosfet and syn- chronous bottom mosfet switches are internal. during normal operation, the internal top power mosfet is turned on each cycle when the oscillator sets the rs latch, and turned off when the current comparator, i comp , resets the rs latch. the peak inductor current at which i comp turns the top mosfet off is controlled by the voltage on the i th pin, which is the output of error amplifier ea. when the load current increases, it causes a slight decrease in the feedback voltage, v fb , relative to the 0.8v internal reference, which, in turn, causes the i th voltage to in- crease until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse direction or the next clock cycle begins. comparator ovdet guards against transient overshoots > 7.5% by turning the main switch off and keeping it off until the fault is removed. burst mode operation the ltc1879 is capable of burst mode operation in which the internal power mosfets operate intermittently based on load demand. to enable burst mode operation, simply tie the sync/mode pin to sv in or connect it to a logic high (v sync/mode > 1.5v). to disable burst mode operation and enable pwm pulse skipping mode, connect the sync/ mode pin to sgnd. in this mode, the efficiency is lower at light loads but becomes comparable to burst mode opera- tion when the output load exceeds 100ma. the advantage of pulse skipping mode is lower output ripple. when the converter is in burst mode operation, the peak current of the inductor is set to approximately 400ma, even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductors average current is greater than the load requirement. as the i th voltage drops below approximately 0.45v, the burst comparator trips, turning off both power mosfets. the i th pin is then disconnected from the output of the ea amplifier and held 0.65v above ground. in sleep mode, both power mosfets are held off and the internal circuitry is partially turned off, reducing the quies- cent current to 15 m a. the load current is now being supplied from the output capacitor. when the output voltage drops, the i th pin reconnects to the output of the ea amplifier and the top mosfet is again turned on and this process repeats. soft-start/run function the run/ss pin provides a soft-start function and a means to shut down the ltc1879. soft-start reduces the input current surge by gradually increasing the regulators maximum output current. this pin can also be used for power supply sequencing. pulling the run/ss pin below 0.7v shuts down the ltc1879, which then draws < 1 m a current from the sup- ply. this pin can be driven directly from logic circuits as shown in figure 1. it is recommended that this pin is driven to v in during normal operation. note that there is no current flowing out of this pin. soft-start action is accom- plished by connecting an external rc network to the run/ ss pin as shown in figure 1. the ltc1879 actively pulls the run/ss pin to ground under low input supply voltage conditions. (refer to block diagram) figure 1. run/ss pin interfacing 3.3v or 5v v in run/ss d1* 0.32v r ss c ss *zetex bat54 1879 f01
9 ltc1879 1879f power good indicator the power good function monitors the output voltage in all modes of operation. its open-drain output is pulled low when the output voltage is not within 7.5% of its nomi- nally regulated voltage. the feedback voltage is filtered before it is fed to a power good window comparator in order to prevent false tripping of the power good signal during fast transients. the window comparator monitors the output voltage even in burst mode operation. in shutdown mode, open drain is actively pulled low to indicate that the output voltage is invalid. short-circuit protection when the output is shorted to ground, the frequency of the oscillator is reduced to about 80khz, 1/7 the nominal frequency. this frequency foldback ensures that the in- ductor current has more time to decay, thereby preventing runaway. the oscillators frequency will progressively increase to 550khz (or to the synchronized frequency) when v fb rises above 0.3v. frequency synchronization the ltc1879 can be synchronized to an external clock source connected to the sync/mode pin. the turn-on of the top mosfet is synchronized to the rising edge of the external clock. when the ltc1879 is clocked by an external source, burst mode operation is disabled. in this synchronized mode, when the output load current is very low, current compara- tor, i comp , may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. increasing the output load slightly allows constant fre- quency pwm operation to resume. frequency synchronization is inhibited when the feedback voltage v fb is below 0.6v. this prevents the external clock from interfering with the frequency foldback for short- circuit protection. low dropout operation when the input supply voltage decreases toward the output voltage in a buck regulator, the duty cycle in- creases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the top mosfet and the inductor. low supply operation the ltc1879 is designed to operate down to an input supply voltage of 2.65v although the maximum allowable output current is reduced at this low voltage. figure 2 shows the reduction in the maximum output current as a function of input voltage. another important detail to remember is that at low input supply voltages, the r ds(on) of the p-channel switch increases. therefore, the user should calculate the power dissipation when the ltc1879 is used at 100% duty cycle with low supply voltage (see thermal considerations in the applications information section). figure 2. maximum output current vs input voltage operatio u (refer to block diagram) input voltage (v) 2 maximum output current (ma) 1200 1400 1600 8 1879 f02 1000 800 4 36 9 57 10 600 400 1800 v out = 1.8v v out = 3.1v v out = 2.5v
10 ltc1879 1879f operatio u slope compensation and inductor peak current slope compensation is required in order to prevent sub- harmonic oscillation at high duty cycles. it is accom- plished by internally adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. as a result, the maximum inductor peak current is reduced for duty cycles > 40%. this is shown in the decrease of the inductor peak current as a function of duty cycle graph in figure 3. figure 3. maximum inductor peak current vs duty cycle applicatio s i for atio wu uu the basic ltc1879 application circuit is shown on the first page of this data sheet. external component selection is driven by the load requirement and begins with the selec- tion of l followed by c in and c out . inductor value calculation the inductor selection will depend on the operating fre- quency of the ltc1879. the internal nominal frequency is 550khz, but can be externally synchronized from 350khz to 750khz. the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, oper- ating at a higher frequency results in lower efficiency because of increased switching losses. the inductor value has a direct effect on ripple current. the ripple current d i l decreases with higher inductance or frequency and increases with higher input voltages. d= ()( ) ? ? ? ? i fl v v v l out out in 1 1 (1) accepting larger values of d i l allows the use of smaller inductors, but results in higher output voltage ripple. a reasonable starting point for setting ripple current is d i l = 0.3(i max ). the inductor value also has an effect on burst mode operation. the transition to low current operation begins when the inductor current peaks fall to approximately 500ma. lower inductor values (higher d i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor selection the inductor should have a saturation current rating greater than the peak inductor current set by the current comparator of ltc1879. also, consideration should be given to the resistance of the inductor. inductor conduc- tion losses are directly proportional to the dc resistance of the inductor. manufacturers sometimes provide maxi- mum current ratings based on the allowable losses in the inductor. suitable inductors are available from coilcraft, cooper, dale, sumida, toko, murata, panasonic and other manu- facturers. duty cycle (%) 0 maximum inductor peak current (ma) 2400 2200 2000 1800 1600 1400 1200 1000 20 40 60 80 1879 f03 100 v in = 5v
11 ltc1879 1879f c in and c out selection in continuous mode, the source current of the top mosfet is a trapezoidal waveform of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms input capacitor current is given by: ii vvv v rms cin omax out in out in () / ( ) @ [] 12 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant devia- tions do not offer much relief. note that the capacitor manufacturers ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there are any questions. depending on how the ltc1879 circuit is powered up, you may need to check for input voltage transients. input voltage transients may be caused by input voltage steps or by connecting the circuit to an already powered up source such as a wall adapter. the sudden application of input voltage will cause a large surge of current in the input leads that will store energy in the parasitic induc- tance of the leads. this energy will cause the input voltage to swing above the dc level of the input power source and it may exceed the maximum voltage rating of the input capacitor and ltc1879. the easiest way to suppress input voltage transients is to add a small aluminum electrolytic capacitor in parallel with the low esr input capacitor. the selected capacitor needs to have the right amount of esr in order to critically dampen the resonant circuit formed by the input lead inductance and the input capacitor. the typical values of esr will fall in the range of 0.5 w to 2 w and capacitance will fall in the range of 5 m f to 50 m f. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment is satisfied, the capacitance is adequate for filtering. the output ripple d v out is determined by: d@d + ? ? ? ? v i esr fc out l out 1 8 where f = operating frequency, c out = output capacitance and d i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since d i l increases with input voltage. for the ltc1879, the general rule for proper operation is: esr cout < 0.125 w the choice of using a smaller output capacitance in- creases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low esr to maintain low ripple volt- age. the i th pin compensation components can be opti- mized to provide stable high performance transient response regardless of the output capacitor selected. manufacturers such as taiyo yuden, avx, kemet and sanyo should be considered for low esr, high perfor- mance capacitors. the poscap solid electrolytic chip capacitor available from sanyo is an excellent choice for output bulk capacitors due to its low esr/size ratio. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. output voltage programming the output voltage is set by a resistor divider according to the following formula: vv r r out =+ ? ? ? ? 08 1 1 2 . (2) the external resistor divider is connected to the output, allowing remote voltage sensing as shown in figure 4. applicatio s i for atio wu uu
12 ltc1879 1879f applicatio s i for atio wu uu if the external frequency (v sync/mode ) is greater than 550khz, the center frequency, current is sourced continu- ously, pulling up the pll_lpf pin. when the external frequency is less than 550khz, current is sunk continu- ously, pulling down the pll_lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pll_lpf pin is adjusted until the phase and frequency of the external and internal oscillators are identical. at this stable operating point the phase com- parator output is open and the filter capacitor c lp holds the voltage. the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter components c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01 m f. when not synchronized to an external clock, the internal connection to the vco is disconnected. this disallows setting the internal oscillation frequency by a dc voltage on the v plllpf pin. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% C ( r 1 + r 2 + r 3 + ...) figure 5. relationship between oscillator frequency and voltage at pll_lpf pin figure 6. phase-locked loop block diagram phase-locked loop and frequency synchronization the ltc1879 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. this allows the mosfet turn-on to be locked to the rising edge of an external frequency source. the frequency range of the voltage-controlled oscillator is 350khz to 750khz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector will not lock up on input frequencies close to the harmonics of the vco center frequency. the pll hold-in range d f h is equal to the capture range, d f h = d f c = 200khz. the output of the phase detector is a pair of complemen- tary current sources charging or discharging the external filter network on the pll_lpf pin. the relationship be- tween the voltage on the pll_lpf pin and operating frequency is shown in figure 5. a simplified block diagram is shown in figure 6. figure 4. setting the ltc1879 output voltage v fb ltc1879 0.8v v out 10v sgnd r2 1879 f04 r1 v plllpf (v) 0 osc frequecny (khz) 1000 900 800 700 600 500 400 300 200 100 0 1879 f05 0.5 1 1.5 2 digital phase/ frequency detector sync/ mode pll_lpf 2.4v c lp 1879 f06 r lp vco
13 ltc1879 1879f where r 1, r 2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in ltc1879 circuits: supply quiescent currents and i 2 r losses. the supply quiescent current loss dominates the efficiency loss at very low load current whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in figure 7. 1. the supply quiescent current is due to two compo- nents: the dc bias current as given in the electrical characteristics and the internal main switch and syn- chronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from pv in to ground. the resulting dq/dt is the current out of pv in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to supply voltage and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches r sw and external inductor r l . in continuous mode the average output current flowing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into sw pins is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteris- tics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply by the square of the average output current. other losses including c in and c out esr dissipative losses, mosfet switching losses and inductor core losses generally account for less than 2% total additional loss. thermal considerations in most applications, the ltc1879 does not dissipate much heat due to its high efficiency. but, in applications where the ltc1879 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction tempera- ture reaches approximately 150 c, both power switches will be turned off and the sw nodes will become high impedance. to avoid the ltc1879 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. normally, some iterative calculation is required to determine a rea- sonably accurate value. the temperature rise is given by: t r = p ? q ja where p is the power dissipated by the regulator and q ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature is given by: t j = t a + t r applicatio s i for atio wu uu figure 7. power lost vs load current load current (ma) 0.1 0.0001 0.001 0.01 0.1 1 power lost (w) 1 10 100 1000 1879 f07 v in = 6v v out = 3.3v l = 6.8 h burst mode operation
14 ltc1879 1879f where t a is the ambient temperature. because the power transistor r ds(on) is a function of temperature, it is usually necessary to iterate 2 to 3 times through the equations to achieve a reasonably accurate value for the junction temperature. as an example, consider the ltc1879 in dropout at an input voltage of 5v, a load current of 0.8a and an ambient temperature of 70 c. from the typical performance graph of switch resistance, the r ds(on) of the p-channel switch at 70 c is 0.38 w . therefore, power dissipated by the ic is: p = i 2 ? r ds(on) = 0.243w for the ssop package, the q ja is 140 c/w. thus the junction temperature of the regulator is: t j = 70 c + (0.243)(140) = 104 c however, at this temperature, the r ds(on) is actually 0.42 w . therefore: t j = 70 c + (0.269)(140) = 108 c which is below the maximum junction temperature of 125 c. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( d i load ? esr), where esr is the effective series resistance of c out . d i load also begins to charge or discharge c out , generating a feedback error signal. the regulator loop then acts to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin can be used for external compensa- tion as shown in figure 9. (the capacitor, c c2 , is typically needed for noise decoupling.) a second, more severe transient is caused by switching in loads with large (> 1 m f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ? c load ). thus, a 10 m f capacitor charging to 3.3v would require a 250 m s rise time, limiting the charging current to about 130ma. applicatio s i for atio wu uu
15 ltc1879 1879f applicatio s i for atio wu uu pc board layout checklist as with all high frequency switchers, when considering layout, care must be taken in order to achieve optimal electrical, thermal and noise performance. figure 8 is a sample of pc board layout for the design example shown in figure 9. a 4-layer pc board is used in this design. several guidelines are followed in this layout: 1. in order to minimize switching noise and improve output load regulation, the pgnd pins of the ltc1879 should be connected directly to 1) the negative terminal of the output decoupling capacitors, 2) the negative terminal of the input capacitor and 3) vias to the ground plane immediately adjacent to pins 1, 7 and 10. the ground trace on the top layer of the pc board should be as wide and short as possible to minimize series resis- tance and inductance. 2. beware of ground loops in multiple layer pc boards. try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. if the ground is to be used for high dc currents, choose a path away from the small-signal components. 3. the high di/dt loop from the top terminal of the input capacitor, through the power mosfets and back to the input capacitor should be kept as tight as possible to reduce inductive ringing. excess inductance can cause increased stress on the power mosfet and increase noise on the input. if low esr ceramic capacitors are used to reduce input noise, place these capacitors close to the dut in order to keep the series inductance to a minimum. 4. place the small-signal components away from high frequency switching nodes. in the layout shown in figure 8, all of the small-signal components have been placed on one side of the ic and all of the power components have been placed on the other. 5. for optimum load regulation and true sensing, the top of the output resistor divider should connect indepen- dently to the top of the output capacitor (kelvin connec- tion), staying away from any high dv/dt traces. place the divider resistors near the ltc1879 in order to keep the high impedance fb node short. figure 8. typical application and suggested layout (topside only) dut r svin r pl pgnd v out v in c out c in2 c in1 l1 r pg c pl c c2 r c c c1 r fb2 r ss c ss r fb1 via connection to r fb1 vias to gnd plane vias to gnd plane 1879 f08
16 ltc1879 1879f applicatio s i for atio wu uu design example as a design example, assume the ltc1879 is used in a dual lithium-ion battery-powered cellular phone applica- tion. the v in will be operating from a maximum of 8.4v down to about 2.65v. the load current requirement is a maximum of 0.7a but most of the time it will be on standby mode, requiring only 2ma. efficiency at both low and high load currents is important. output voltage is 2.5v. with this information we can calculate l using equation (1), l fi v v v l out out in = () d () ? ? ? ? 1 1 (3) substituting v out = 2.5v, v in = 8.4v, d i l = 210ma and f = 550khz in equation (3) gives: l v khz ma v v h = ? ? ? ? =m 25 550 210 1 25 84 15 2 . . . . an 15 m h inductor works well for this application. for good efficiency choose a 1.5a inductor with less than 0.125 w series resistance. c in will require an rms current rating of at least 0.35a at temperature and c out will require an esr of less than 0.125 w . in most applications, the requirements for these capacitors are fairly similar. for the feedback resistors, choose r2 = 412k. r1 can then be calculated from equation (2) to be: r v r k use k out 1 08 1 2 875 5 887 = ? ? ? ? = . ., figure 9 shows the complete circuit along with its effi- ciency curve.
17 ltc1879 1879f figure 9a. dual lithium-ion/8v wall adapter to 2.5v/0.7a regulator from design example applicatio s i for atio wu uu figure 9b. efficiency vs output current for design example 5 12 6 11 3 1 1879 f09a swp swp swn swn v fb i th r c 150k pll_lpf run/ss pgood sgnd 8 9 pv in pv in 7 10 pgnd pgnd sync/mode r svin 10 ltc1879 l1 15 h v out 2.5v 0.7a v in 2.65v to 8.4v gnd r1 887k r2 412k c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f c c1 47pf bold lines indicate high current paths c c2 220pf c in1 , c in2 : taiyo yuden ceramic jmk316bj106ml c out : tdk ceramic c4532x5r0j476m l1: toko a921cy-150m v out : 0.7a is the maximum output current r ss 1m r pg 100k c ss 0.1 f c in2 10 f output current (ma) 70 efficiency (%) 80 100 0.1 10 100 1000 1879 f09b 60 1 90 v in = 3.6v v out = 2.5v l = 15 h
18 ltc1879 1879f typical applicatio u dual li-ion to 1.8v/1a regulator using all ceramic capacitors 5 12 6 11 3 1 1879 ta02 swp swp swn swn v fb i th r c 150k pll_lpf run/ss pgood sgnd 8 9 pv in pv in 7 10 pgnd pgnd sync/mode r svin 10 ltc1879 l1 8.2 h v out 1.8v 1a v in 3v to 8.4v gnd c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f c c1 47pf bold lines indicate high current paths c c2 220pf c in1 , c in2 : taiyo yuden ceramic lmk325bj106mn c out : tdk ceramic c4532x5r0j476m l1: toko a916cy-8r2m v out : 1a is the maximum output current r ss 1m r pg 100k c ss 0.1 f c in2 10 f r1 523k r2 412k output current (ma) 60 efficiency (%) 80 100 50 70 90 0.1 10 100 1000 1879 ta04 40 1 v in = 3.6v v in = 7.2v v in = 5v v out = 1.8v burst mode operation efficiency vs output current
19 ltc1879 1879f package descriptio n u gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
20 ltc1879 1879f ? linear technology corporation 2001 lt/tp 0303 2k ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio u 5-cell nimh to 3.3v/0.25a zeta regulator using all ceramic capacitors 5 12 6 11 3 1 1879 ta03 swp swp swn swn v fb i th r c 150k pll_lpf run/ss pgood sgnd 8 9 pv in pv in 7 10 pgnd pgnd sync/mode r svin 10 ltc1879 l1 4.7 h l1 v out 3.3v 0.25a v in 2.8v to 7.5v gnd c in1 10 f c out 47 f 15 13 14 2 16 4 sv in c svin 0.1 f c c1 47pf bold lines indicate high current paths c c2 220pf c c : taiyo yuden ceramic lmk325bj106mn c in1 , c in2 : taiyo yuden ceramic lmk325bj106mn c out : tdk ceramic c4532x5r0j476m l1: coiltronics ctx5-4 r ss 1m r pg 100k c ss 0.1 f c in2 10 f c c 10 f r1 1.3m r2 412k related parts part number description comments lt1616 25v, 500ma (i out ), 1.4mhz, high efficiency v in = 3.6v to 25v, v out(min) = 1.25v, i o = 1.9ma, i sd = <1 m a, thinsot tm step-down dc/dc converter lt1676 60v, 440ma (i out ), 100khz, high efficiency v in = 7.4v to 60v, v out(min) = 1.24v, i o = 3.2ma, i sd = 2.5 m a, so-8 step-down dc/dc converter lt1765 25v, 2.75a (i out ), 1.25mhz, high efficiency v in = 3v to 25v, v out(min) = 1.20v, i o = 1ma, i sd = 15 m a, so-8, tssop16e step-down dc/dc converter lt1766/lt1956 60v, 1.2a (i out ), 200khz/500khz, high efficiency v in = 5.5v to 60v, v out(min) = 1.20v, i o = 2.5ma, i sd = 25 m a, tssop16/e step-down dc/dc converter lt1767 25v, 1.2a (i out ), 1.25khz, high efficiency v in = 3v to 25v, v out(min) = 1.20v, i o = 1ma, i sd = 6 m a, so-8, ms8/e step-down dc/dc converter ltc ? 1875 1.5a, (i out ), 550khz, synchronous step-down v in = 2.7v to 6v, v out(min) = 0.8v, i o = 15 m a, i sd = <1 m a, tssop-16 dc/dc converter ltc1877 600ma, (i out ), 550khz, synchronous v in = 2.7v to 10v, v out(min) = 0.8v, i o = 10 m a, i sd = <1 m a, ms8 step-down dc/dc converter lt1940 dual output 1.4a (i out ), constant 1.1mhz, v in = 3v to 25v, v out(min) = 1.2v, i o = 2.5 m a, i sd = <1 m a, tssop-16e high efficiency step-down dc/dc converter ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous v in = 2.7v to 6v, v out(min) = 0.8v, i o = 20 m a, i sd = <1 m a, thinsot step-down dc/dc converters ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous v in = 2.5v to 5.5v, v out(min) = 0.6v, i o = 20 m a, i sd = <1 m a, thinsot step-down dc/dc converters ltc3411 1.25a (i out ), 4mhz, synchronous v in = 2.5v to 5.5v, v out(min) = 0.8v, i o = 60 m a, i sd = <1 m a, 10-pin ms step-down dc/dc converter ltc3412 2.5a (i out ), 4mhz, synchronous v in = 2.5v to 5.5v, v out(min) = 0.8v, i o = 60 m a, i sd = <1 m a, tssop16e step-down dc/dc converter ltc3430 2.5a (i out ), 4mhz synchronous v in = 2.5v to 5.5v, v out(min) = 0.8v, i o = 60 m a, i sd = <1 m a, tssop16e step-down dc/dc converter thinsot is a trademark of linear technology corporation.

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